1. Technical Field
This disclosure generally relates to computer hardware testing and development, and more specifically relates to a system and method for replicating test data into memory cache with non-naturally aligned data boundaries while preserving sub-segments with aligned boundaries in the segments of the replicated test data.
2. Background Art
Processor testing tools exist whose goal is to generate the most stressful test case for a processor. In theory, the generated test case should provide maximum test coverage and should be able to stress various timing scenarios on the processor, including the memory. Building test cases can be extremely costly in time and resources such that building efficient test cases is an important part of processor testing.
Many processors have restrictions on alignment for memory operations. For example, some power processors allow different alignment boundaries in memory for different instructions while in different modes like Cache Inhibited, Little Endian etc. With these complexities on boundary restrictions, it's very difficult to generate test cases for the different alignment boundaries for each of the instructions. Moreover, testing all valid boundaries for an instruction is very important and multiple test cases for multiple boundaries would have the overhead of generation and simulation in case of reference model checking. Prior art test case generation was extremely labor intensive to test the different alignment boundaries while preserving boundaries where needed.